This invention relates to oscillator circuits.
Current mode control integrated circuits, for use in fixed-frequency power supply applications require as one of the circuit functions, an oscillator that can be easily programmed to provide a precise timing signal. The need for a precise timing signal is two-fold. In order to minimize the power supply output voltage ripple, filtering components are chosen for the nominal operating frequency. Any deviation from the nominal frequency will result in increased output ripple. Secondly, it is necessary to limit the maximum on-time of the switching transistor in order to prevent core saturation and ultimately a catastrophic failure.
The oscillator should also be capable of several decades of operating frequencies in order to be useful in many applications. As the switching times of the external components are reduced, higher oscillator frequencies are required to take advantage of the smaller filtering components associated with high frequency operation.
A relaxation oscillator of the prior art in its simplest form is shown in FIG. 1. Transistor 10 and transistor 11 form a comparator. The base of transistor 10 is connected to an RC terminal 22. A timing capacitor 12 and a charging resistor 13 are connected to the oscillator circuit at the RC terminal 22. A transistor 17 has an emitter connected to the voltage supply terminal 14. A resistor 23 is connected between the emitter and the base of transistor 17. Another resistor 24 is connected at one end to the collector of transistor 17, the base of a transistor 15 and the base of a transistor 16. The other end of resistor 24 is connected to ground.
The timing capacitor 12 is charged through the charging resistor 13 towards the voltage at the voltage supply terminal 14. While the capacitor 12 is charging, transistor 15, transistor 10, transistor 16 and transistor 17 are non-conducting. The base of transistor 11 is at the upper voltage limit of the oscillator waveform as determined by resistors 18 and 19. When the voltage on the timing capacitor 12 reaches the upper voltage limit, transistor 10 turns on and transistor 11 turns off. This causes transistor 17, transistor 15, and transistor 16 to fully conduct.
Transistor 16 essentially places a resistor 20 in parallel with resistor 19 thereby lowering the voltage at the base of transistor 11 to the bottom voltage of the oscillator waveform. With transistor 15 on, a discharging resistor 21 will provide a discharge path for the timing capacitor 12. When the timing capacitor 12 has a potential which has dropped to the bottom voltage, transistor 11 turns on and transistor 10 turns off and the cycle repeats.
While this simple oscillator has been implemented in many circuit designs, it suffers from a number of deficiencies. There is often caused an error in the bottom voltage of the waveform. When transistor 16 turns on, there is a voltage drop across its collector to emitter, the saturation voltage. This voltage varies due to manufacturing tolerances and operating temperature. Present manufacturing techniques tolerate a 30% error in the saturation voltage across a transistor in an integrated circuit. The error caused by providing a transistor 16 in the resistor network which determines the bottom voltage of the waveform is most troublesome when the supply voltage 14 is low.
There may also be an error in the discharge current which causes an error in the timing of the waveform. The collector-emitter voltage of transistor 15 when turned on can introduce an error in the amount of discharge current that is available through the discharge resistor 21.
Especially noticeable at high operating frequencies is the problem of propagation delay error. When the voltage on timing capacitor 12 voltage drops to the bottom voltage, transistor 15 and transistor 16 should ideally turn off instantly allowing the capacitor to start charging. However, since transistor 15 and transistor 16 have been operating in the saturation region, there is a finite time required to completely turn them off. Thus the capacitor will continue to discharge below the bottom voltage. The higher the operating frequency the more pronounced this error becomes because under high frequency operation the voltage is changing more quickly.
A further disadvantage of this prior art circuit is that it has a dependence on a propagation delay. If transistor 15 were able to switch much faster than transistor 16, as soon as the capacitor voltage reached the top voltage, transistor 15 would turn on causing the capacitor voltage to decrease before transistor 16 was able to turn on. The oscillator would then assume a stable state with the capacitor voltage near the top voltage. To guarantee switching, a delay must be designed into transistor 15 to insure that transistor 16 turns on to change the comparator reference voltage before the capacitor is discharged. In the prior art designs, the discharge transistor 15 is generally made larger in size than transistor 16. This causes transistor 16 to switch faster than transistor 15 insuring that the threshold will change before the capacitor charge-to-discharge cycle begins. This dependence of the prior art circuit upon propagation delay for reliable operation causes absolute frequency shifts at higher frequencies thereby limiting the operation of these circuits to a lower frequency range.
In certain applications, it is desirable to connect two or more controllers in parallel to increase the output power capabilities. This requires one of the controller's oscillator circuits to act as the master while the other controllers are slaves. A method of synchronizing the frequency of the slaves to the master is required. A plurality of prior art oscillator circuits cannot simply be connected at their RC terminals 22. Because of manufacturing tolerances the top and bottom thresholds are different for each of the oscillators. Therefore, if the RC terminal is used for all of the oscillators only the oscillator with the lowest top or highest bottom voltage would actually switch states. In the prior art to remedy this situation, oscillators usually included a separate synchronizing input/output terminal to provide a well-defined clock pulse which would cause all of the oscillators to switch simultaneously. The disadvantage of this scheme is that additional circuitry and an additional device pin are required for its implementation.